The cost of designing a computer processor continues to increase. Some computer architectures thus ultimately become uneconomical to implement directly, despite these architectures having significant installed bases.
One solution to this problem is to simulate one computer architecture on another computer architecture. Herein, the simulating computer architecture will be termed the “host” computer system, while the simulated computer architecture will be termed the “target” computer system. Emulators have been available almost since the advent of the first compilers.
Emulators typically utilize the same word length and byte length on the host computer system and the target computer system. One reason for this is that it is significantly easier to implement a similar system emulator. Another reason is that most computer architectures presently are 32-bit architectures. However, there is a move toward 64-bit architectures. Two 32-bit words fit exactly within a single 64-bit word. This is not the situation where the target system operates on for example 36 bits, while the host system operates on 64 bits. Any problems encountered when implementing an emulator on a host system are significantly increased when the word size of the emulated target system does not evenly divide the word size of the host system.
When the two architectures have different word sizes the data type alignment of the target data in the emulated host memory will not align with the native data types in the host emulation machine. This is particularly a problem in multiprocessor emulations that require atomicity for updates of adjacent target data types within a cache line of the emulating host system memory. The atomicity of the emulating host system will not match the required atomicity of the emulated target system. This is because the atomicity paradigms of the host system will not properly merge the updates within a cache line.
This would normally be addressed by use of a separate software gating mechanism. A distinct gate would be employed by each instance of the processor emulation in order to perform any data update to the emulated memory where atomicity needed to be enforced. Such a software gating mechanism typically employs hardware instructions to lock and unlock an agreed-to gate operand in order to guarantee single-threaded operation. This software gating mechanism has the potential of adding significant processor, memory, and bus overhead to the operation of the emulator.
The problem is compounded when it is necessary to read and write double words. Double word reads and writes are common in many legacy architectures. It is possible with single word synchronization to have a situation where the first and second words in a double word write are written by two different processors at almost exactly the same time. This would necessarily lead to inconsistent results.
Double word read and write atomicity is important in many architectures and systems. In the preferred embodiment, in the emulation of the GCOS 8 operating system on a target architecture such as the Intel IA-64 architecture that does not fully support double (or more) atomic reads and writes, atomic double word reads and writes are important in maintaining system security since system security is built around double word descriptors. Lack of double (or more) word atomicity may open up significant security holes in the GCOS 8 operating systems.
It would thus be advantageous to be able to emulate efficiently a target system that has a word size and/or byte size that is not the same as that of the emulating host system. It would be even more advantageous to be able to emulate efficiently such a system when the word size of the host system is not an even multiple of the word size of the emulated target system. In performing this emulation, an efficient mechanism for reading and writing double word cached memory contents without violating atomicity constraints of an emulated target system would also be advantageous.